Wirings for checking, pads and wirings called as short rings, which are necessary in the manufacture process of an array substrate for a display device of a liquid crystal display device, are arranged on periphery regions of the array substrate of a display device. The wirings called as short rings refer to wirings that make scan lines and signal lines short-circuited, allowing for destroys caused by static electricity occurred in the manufacture process.
In the periphery regions, in order to short-circuit scan lines and signal lines, through-holes are needed since the scan lines and the signal lines exist in different layers with an insulation layer sandwiched therebetween. Conventionally, through-holes are provided to directly connect the scan lines and the signal lines. FIG. 5 is a schematic cross sectional view for illustrating a through-hole directly connecting a scan line and a signal line. In FIG. 5, 303 denotes an ITO (Indium Tin Oxide) layer serving as a transparent electrode layer, 105 denotes a signal line layer, 101 denotes a scan line layer, and 701 denotes a through-hole arranged between the scan line layer and the signal line layer.
But in recent years, in order to reduce photolithography processes, through-holes are not used to directly connect scan lines and signal lines, but are formed on scan lines and signal lines at first, then an ITO layer is filled in the through-holes, thereby the scan lines and the signal lines are connected through the ITO layer. The manufacture process mentioned above is gradually popularized. The description is made herebelow in conjunction with the drawings.
FIG. 3 is a schematic cross sectional view of an array substrate, which is made by the above mentioned manufacture process and in which scan lines and signal lines are connected through an ITO layer. In FIG. 3, 303 denotes an ITO layer, 101 denotes a scan line, 105 denotes a signal line, 102 denotes a through-hole arranged on the scan line 101, into which the ITO layer is filled, 104 denotes a through-hole arranged on the signal line 105, into which the ITO layer is filled similarly. P1 is a point in the part of the scan line layer 101 abutting the scan line layer through-hole 102, which is the nearest point to the signal line layer through-hole 104. P2 is a point in the part of the signal line layer 105 abutting the signal line layer through-hole 104, which is the nearest point to the through-hole 102 on the scan line layer.
In FIG. 3, instead of directly connecting with each other, the scan line 101 and the signal line 105 are connected through the ITO layer 303. This type of connection can reduce photolithography processes and manufacture cost.
However, since the resistance rate of the ITO layer is not low enough, the resistance of the ITO layer between the point P1 and the point P2 may not be neglectable when the resistance between the through-hole 102 and the through-hole 104 is taken in account. The value of connection resistance between the scan line 101 and the signal line 105, when the scan line 101 and the signal line 105 are connected via the through-holes 102 and 104, mainly depends on the resistance value of the ITO layer between the point P1 and the point P2. In addition, the resistance value of the ITO layer between the point P1 and the point P2 is directly proportional to the length of the ITO between the point P1 and the point P2.
Related information has also been specifically disclosed in Patent Document 1: Japanese Patent Laid-Open Publication No. 8-122819.
Hence, in order to reduce the resistance value between the through-hole 102 and the through-hole 104, it is required to reduce the length between the point P1 and the point P2 as short as possible.